search

YosysHQ / yosys

Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
3.3k stars 860 forks source link

ERROR: parsing SystemVerilog Attribution #792

Open lvcargnini opened 5 years ago

lvcargnini commented 5 years ago

Steps to reproduce the issue

Provide instructions for reproducing the issue. Make sure to include all necessary source files. (You can simply drag&drop a .zip file into the issue editor.) Hello I tried to synthesize an example code, the DDF-OK, Register-OK, Adder-FAILED files.zip

Just open yosys and run read_verilog -sv for each file, dff, register, and adder

Expected behavior

Please describe the behavior you would have expected from the tool. The expected was to have it synthesized

Actual behavior

Observing the error Message it was the following: yosys> read_verilog -sv ../rtl/adder.sv

  1. Executing Verilog-2005 frontend. Parsing SystemVerilog input from `../rtl/adder.sv' to AST representation. ../rtl/adder.sv:38: ERROR: syntax error, unexpected $undefined

The Error line it is: result <= '{default:0}; This is a SystemVerilog to attribute values of any format, all bits on same value like if it was vec[31:0][0:12][1:9], this format could set zero in all bits

Please describe how the behavior you see differs from the expected behavior.

Important Note: Nobody will be able to help you and/or fix the issue if you do not provide sufficient information for reproducing the problem.

eddiehung commented 5 years ago

Unfortunately, Yosys does not have full SV support, and this case looks like one which succumbs to that category. Marking as enhancement.