There is a bug in your code

[dys-yushengzhai]

‘’‘ module testA (A,B,Y); input A,B; output Y; wire Y; // assign Y = ~(A&B);

endmodule

module testB (A,B,Y); input A,B; output Y; wire Y; // assign Y = A & B;

endmodule ’‘’ write_edgelist testA.el write_edgelist testB.el testA.el and testB.el is the same

[ycunxi]

Thanks for checking our tool. First of all, it is not a bug. Here is why:

The graphs in AIG of these two designs are indeed identical. Note that our intermediate representation for the graph structure in AIG mode is structural hashed by ABC (see strash in ABC command)

Instead, if you want to make these two designs ''different'', you need to use a structural Verilog w.r.t a given technology library.

[dys-yushengzhai]

Thank for your reply. My biggest question is why don't you let the Po node carry infomation. For example: 1 4 Pi 00 2 5 Pi 00 4 7 AIG 11 5 7 AIG 11 7 3 Po x if x==0 not if x==1 buffer if x==2 wire Will this greatly affect the speed?

------------------ 原始邮件 ------------------ 发件人: "Yu-Maryland/Verilog-to-PyG" @.>; 发送时间: 2024年3月26日(星期二) 上午9:15 @.>; @.**@.>; 主题: Re: [Yu-Maryland/Verilog-to-PyG] There is a bug in your code (Issue #1)

Thanks for checking our tool. The graphs in AIG of these two designs are indeed identical. Note that our intermediate representation for the graph structure in AIG mode is structural hashed by ABC (see strash in ABC command)

Instead, if you want to make these two designs ''different'', you need to use a structural Verilog w.r.t a given technology library.

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