How to simulate the generated verilog

[ghost]

Hi,

I don't have the hardware ... but I'm interested to compare speedup of result's to understand the code and get an estimate. Can you please tell me how can I do that ?

thanks, Tarun

[ZFTurbo]

You can try to use testbench:

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/verilog/code/testbench.v

[ghost]

Hi I tried to simulate testbench.v using xcelium by using

xrun -f testbench.v

I encountered the following error :

xrun: E,FMUK: The type of the file (storage[777]) could not be determined. xrun: E,FILEMIS: Cannot find the provided file storage[777]. xrun: E,FMUK: The type of the file (=) could not be determined. xrun: E,FILEMIS: Cannot find the provided file =. xrun: E,FMUK: The type of the file (11'b10010111000;) could not be determined. xrun: E,FILEMIS: Cannot find the provided file 11'b10010111000;. xrun: E,FMUK: The type of the file (storage[778]) could not be determined. xrun: E,FILEMIS: Cannot find the provided file storage[778]. xrun: E,FMUK: The type of the file (=) could not be determined. xrun: E,FILEMIS: Cannot find the provided file =. xrun: E,FMUK: The type of the file (11'b10010101000;) could not be determined. xrun: E,FILEMIS: Cannot find the provided file 11'b10010101000;. xrun: E,FMUK: The type of the file (storage[779]) could not be determined. xrun: E,FILEMIS: Cannot find the provided file storage[779]

I'm new in field of electronics ... can you suggest How can I run this.

thanks

congrats for the great work, best wishes

[ZFTurbo]

Do you have access to ModelSim? If I remember we use it for testing.

[ghost]

Hi,

No... I don't have its licence. I only have xcelium.

thanks

[ghost]

I think this is due to not able to access TOP.v file in neuroset. it doesn't include all the .v modules.

thanks

[ZFTurbo]

As I know ModelSim is avilable for free: https://fpgasoftware.intel.com/?product=modelsim_ae#tabs-2

I can't help you with xcelium. Probably you need to include all needed .v files in testbench somehow.

[ghost]

Thnaks for the modelsim ... I can give a try. Also I have more query regarding the input image in testbench.v , from which path it's picking its image.

thanks, Tarun

[ZFTurbo]

It's hardcoded in initial block. See "storage" variable

[ghost]

Hi, is there any way we can read the image directly by converting it into some format. also, is this conversion of 11 bits or 10 bits is in testbench is also dynamic based on your previous stage results?

thanks

[ZFTurbo]

Bit for image is found in "r03_find_optimal_bit_for_weights.py". Also there was some code I used to convert PNG to this format used in testbench. I will try to find it.

[ghost]

thanks, Please check and let me know. this will be good so we can see that the output of the simulation is with respect to which image.

thanks

[ghost]

Hi,

One more doubt, the testbench.v is written for :

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/verilog/code/neuroset/TOP.v

this file right ?

thanks

[ZFTurbo]

Yes, must be for TOP

[ghost]

Hi,

thanks for your advice ... with some modification, I'm able to finally simulate :) however, previous error in the compilation is because in neroset/conv_TOP.v file, the parameter conv 3 is not set. also while simulation is working and result is always 10 and it throws msgs Overflow in conv !.

why result is everytime 10, is it because everytime same test image is hardcoded into testbench.v file ? can you please check.

thanks

[ghost]

Hi,

Congrats, the .py files generating verilog files are written with such precision ... I mean a small change could cause a lot hard to determine errors of the generated files.

kudos for this great work :)

thanks

[ZFTurbo]

I added code to convert image to testbench format: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/utils/convert_image_for_testbench.py

[ghost]

Hi,

thanks for adding the file. it's really helpful. Can we use optimal bit setting +1 extra bit to prevent overflow in neuroset/conv.v file?

thanks

[ZFTurbo]

If you change optimal bit you need to regenrate all files with this optimal bit. Including image in test_bench.

[ghost]

Hi,

thanks for your advice ... with some modification, I'm able to finally simulate :) however, previous error in the compilation is because in neuroset/conv_TOP.v file, the parameter conv on line 3 is not set. also while simulation is working and result is always 10 and it throws msgs Overflow in conv !.

why result is everytime 10, is it because everytime same test image is hardcoded into testbench.v file ? can you please check.

thanks

hi, is there any particular reason for not setting this parameter num_conv in conv_TOP.v file on line 3 ... Can you please check as this is causing a syntax error while simulation. I fixed this in my local directory but I'm curious about the reason.

thanks

[ghost]

I added code to convert image to testbench format: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/utils/convert_image_for_testbench.py

hi,

the test bench consists of only

Initial begin storage[0] = 11'b10011110000 storage[0] = 11'b10101110000 ...... ...... end

only and not instantiate the module and other parameters which is why the generated testbench can't be simulated. I tried to find the part of code that is doing this but didn't get anything. is this part is constant ?

thanks

[ZFTurbo]

You need to replace only image part in current testbench. Generator only generate image description without other testbench stuff.

[ZFTurbo]

hi, is there any particular reason for not setting this parameter num_conv in conv_TOP.v file on line 3 ... Can you please check as this is causing a syntax error while simulation. I fixed this in my local directory but I'm curious about the reason.

It's probably because this parameter is set in TOP module.

module TOP(clk, GO, RESULT, we_database, dp_database, address_p_database, STOP);

parameter num_conv = 1;

[ghost]

Hi,

why are train and test data consist of folder 10 is it for background while analyzing real data through the camera , in standard MNIST dataset ... we don't consider that class. also training images of dimension 28x28 but testing images are of dimension 320x240.

thanks,

[ZFTurbo]

In MNIST dataset each class contain number, but in real world we have images without any number on it. So we add additional class for 'no number' class. Also image from camera have other resolution. In our case it's 320x240. Test folder contains raw images obtained from device camera.

[ghost]

Hi,

thanks for the above explanation... I was expectating something similar. Can you please tell me what is the usage of r04_verilog_generator_grayscale_file.py and verilog/code/gray_28x28/grayscale.v

do I need to include this file during simulation or not as we already providing an RGB image in testbench?

thanks

[ZFTurbo]

As I remember this module converts RGB image from camera to 28x28 size.

[ghost]

Do I need to include it while running the simulation ?

thanks

[ZFTurbo]

I don't think so, because in tesetbench you already use grayscale image 28x28.

[ghost]

what is the use of the /verilog/imp folder and /verilog/code/lcd and /verilog/code/synt folders ?

thanks

[ZFTurbo]

/verilog/imp - mostly files generated by Quartus for FIFO and PLL, also some top level project files /verilog/code/lcd - verilog files for LCD-screen /verilog/code/synt - verilog to interact with camera, working with SDRAM, FIFO to input/output data from camera and memory.