Terasic DE10-Lite - Githubissues

ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

Apache License 2.0

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Open Bahadiirr opened 3 years ago

Bahadiirr commented 3 years ago

Does the project work in Terasic DE10-Lite? The board have max10 FPGA chip

ZFTurbo commented 3 years ago

We didn't check, but I think it should work.