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ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA
Apache License 2.0
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About Testbench.v Result #17

Closed QiQi-OvO closed 2 years ago

QiQi-OvO commented 3 years ago

Why do I generate results that don't match the actual results Answer:.

QiQi-OvO commented 3 years ago

Hi, and I want to know the meaning of variables: memstartp,memstartzap,mem,filt,matrix,lvl,slvl,num. thanks a lot

kangliyu1 commented 2 years ago

Why do I generate results that don't match the actual results Answer:.

Hello, I also encountered the problem that the simulation does not match the results. Can you give me some pointers on how to solve it? Many thanks

QiQi-OvO commented 2 years ago

你可以试着调一下时钟频率，我记得时钟频率好像会影响到整个结果。过去的时间比较久，我已经不再做这个方面的研究了。

------------------ 原始邮件 ------------------ 发件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA" @.>; 发送时间: 2022年1月10日(星期一) 下午2:51 @.>; @.>;"State @.>; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA] About Testbench.v Result (#17)

Why do I generate results that don't match the actual results Answer:.

Hello, I also encountered the problem that the simulation does not match the results. Can you give me some pointers on how to solve it? Many thanks

— Reply to this email directly, view it on GitHub, or unsubscribe. Triage notifications on the go with GitHub Mobile for iOS or Android. You are receiving this because you modified the open/close state.Message ID: @.***>

kangliyu1 commented 2 years ago

你可以试着调一下时钟频率，我记得时钟频率好像会影响到整个结果。过去的时间比较久，我已经不再做这个方面的研究了。 … ------------------ 原始邮件 ------------------ 发件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA" @.>; 发送时间: 2022年1月10日(星期一) 下午2:51 @.>; @.>;"State @.>; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA] About Testbench.v Result (#17) Why do I generate results that don't match the actual results Answer:. Hello, I also encountered the problem that the simulation does not match the results. Can you give me some pointers on how to solve it? Many thanks — Reply to this email directly, view it on GitHub, or unsubscribe. Triage notifications on the go with GitHub Mobile for iOS or Android. You are receiving this because you modified the open/close state.Message ID: @.***>

好的谢谢您的回复，还有个问题就是想问下您，那您怎么知道自己调完时钟频率之后仿真就会对了，他的testbench里的784个11位的storage是代表的什么数呢？那您知道它自带的那个testbench的storage这个784个11位的数是怎么生成的吗？是使用它的哪个python生成的吗？您是单独仿真他的神经网络加速器还是整个带摄像头的工程呢？

kangliyu1 commented 2 years ago

你可以试着调一下时钟频率，我记得时钟频率好像会影响到整个结果。过去的时间比较久，我已经不再做这个方面的研究了。 … ------------------ 原始邮件 ------------------ 发件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA" @.>; 发送时间: 2022年1月10日(星期一) 下午2:51 @.>; @.>;"State @.>; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA] About Testbench.v Result (#17) Why do I generate results that don't match the actual results Answer:. Hello, I also encountered the problem that the simulation does not match the results. Can you give me some pointers on how to solve it? Many thanks — Reply to this email directly, view it on GitHub, or unsubscribe. Triage notifications on the go with GitHub Mobile for iOS or Android. You are receiving this because you modified the open/close state.Message ID: @.***>

我是想单独仿真验证它的神经网络加速器的代码，但是刚刚在testbench中更改频率（改动了clk）之后发现结果并没有发现变化，如果您有空的话希望可以指点一下，万分感谢前辈