The result of testbench doesn't match with the actual result

ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

Apache License 2.0

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The result of testbench doesn't match with the actual result #18

Closed hithere124 closed 2 years ago

hithere124 commented 3 years ago

Hi, I used the _convert_image_fortestbench.py to convert the image and then replaced the image part in testbench.v But when I run the simulation, the result doesn't match with the input image, can you please check it again?

ZFTurbo commented 2 years ago

Looks like we solved it. Sorry for long response: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/21