Timing Simulation not working

ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

Apache License 2.0

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Timing Simulation not working #19

Open zee9999 opened 2 years ago

zee9999 commented 2 years ago

First of all, this project is really good. We ran the functional simulation on ModelSim and worked perfectly however when we ran the timing simulation-after the synthesis on Quartus lite-it kept giving us a RESULT"1111" for a while and no output was given after that. Here is a link with the timing simulation

ZFTurbo commented 2 years ago

The verilog code author says it's ok. Can you check the end of waveform?

kangliyu1 commented 2 years ago

@zee9999 @ZFTurbo Hi, I also encountered this problem, have you solved it? Can you give me some pointers? Many thanks! !

ZFTurbo commented 2 years ago

Looks like we solved it. Sorry for long response: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/21