the question of verilog code generator

[xw2333]

Hello, I would like to ask you a question, your py code to generate verilog code, is actually just some import of weights?The timing of the verilog code is still a lot of work, right?

[ZFTurbo]

No. The py code create full verilog description of neural net, including convolution blocks, other layers description, control module etc.

[xw2333]

Thank you for your letter. Could you please send me the reference document of your verilog code design and detailed comments, because your code is still difficult for me to understand。With best wishes!

------------------ 原始邮件 ------------------ 发件人: "ZFTurbo"notifications@github.com; 发送时间: 2018年9月7日(星期五) 晚上10:38 收件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA"Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA@noreply.github.com; 抄送: "Laplace"1010944344@qq.com; "Author"author@noreply.github.com; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA]the question of verilog code generator (#2)

No. The py code create full verilog description of neural net, including convolution blocks, other layers description, control module etc.

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[ZFTurbo]

It was experimental verilog code, mostly made by unexperienced people in that field. We didn't make detailed documentation for it. ( And we currently have no plans and resources to do refactoring of verilog, since switched on other task. Sorry.

I plan to release other project involving Verilog code for Neural Nets with better comment section and documentation.

[xw2333]

When and where can I see the verilog code related to neural network?Thank you very much!

------------------ 原始邮件 ------------------ 发件人: "ZFTurbo"notifications@github.com; 发送时间: 2018年9月26日(星期三) 下午5:56 收件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA"Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA@noreply.github.com; 抄送: "Laplace"1010944344@qq.com; "Author"author@noreply.github.com; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA]the question of verilog code generator (#2)

It was experimental verilog code, mostly made by unexperienced people in that field. We didn't make detailed documentation for it. ( And we currently have no plans and resources to do refactoring of verilog, since switched on other task. Sorry.

I plan to release other project involving Verilog code for Neural Nets with better comment section and documentation.

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[xw2333]

Is this code working properly?Because I've been analyzing this code recently, there's a lot that I don't quite understand.Thank you very much.

[ZFTurbo]

Code was tested on real device. It works. I will check the latest version one more time to ensure.

[xw2333]

Thank you very much. I hope you can provide some reference documents for us to understand.

[ZFTurbo]

I checked the latest version from repository on our device. It works fine (just ensure you have ehough light in room). I have a question: Did you create the same hardware device as we propose or you just try to learn verilog code?

[xw2333]

Thank you for your letter. I don't have the same hardware as you. I tested on another fpga and found that the work was ok when conv-num=1. But an error occurred when conv-num=4. I looked at your code and found that there were many problems with the synthesized circuit. I plan to make a neural network IP core, so learn your code! Thank you very much!

[xw2333]

I hope you can give me some guidance. Best wishes

[ZFTurbo]

I have one guess. Since you use other FPGA then critical path is different, so you probably need to decrease frequency in quartus project. I will ask the colegue who was responsible for verilog code.

[Aobo-xd]

I am a student and I just want to learn some idea about the neural network knowledeg about verilog. I want to search a way to improve the performance of the my neural network. I had read the parper about you work. Many problem puzzled a lot. As Andrew Ng saying, bias is important for the neural network, how do you cut it down and get imageable result. Can you explain it to me? thank you very much.Best wishes.

[ZFTurbo]

For this particular work during experiments we found out that neural net was trained ok without bias. I'm not sure if it will be fine for some more complex problem. From my experience i'd propose the following changes: 1) Add BatchNormalization layers after Conv2D blocks (Conv2D blocks can be used without bias). After training when you have weights you can merge these blocks together in single Conv2D blocks. See: https://raw.githubusercontent.com/ZFTurbo/Keras-inference-time-optimizer/master/img/conv_bn_fusion.png The training will be more stable and you will have better accuracy comparing to "no bias" case. 2) It's good idea to use ReLU with limit from the TOP, like it was made in MobileNet. It will be much easier to move to fixed point representation of neural net.

[xw2333]

May I trouble you again,, could you please provide some references to help us better understand the verilog code?Because the code is so poorly understood for me without any reference

[ZFTurbo]

@xw2333 there is no reference or documentation for verilog code. It was provided as is.

[xw2333]

thank you.

------------------ 原始邮件 ------------------ 发件人: "ZFTurbo"notifications@github.com; 发送时间: 2018年10月15日(星期一) 晚上8:31 收件人: "ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA"Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA@noreply.github.com; 抄送: "Laplace"1010944344@qq.com; "Mention"mention@noreply.github.com; 主题: Re: [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA]the question of verilog code generator (#2)

@xw2333 there is no reference or documentation for verilog code. It was provided as is.

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[baogiadoan]

i tried to use the same hardware as yours, but when I compile the project in Quartus and it has this error: Error (12006): Node instance "maxpooling" instantiates undefined entity "maxp". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP. I don't know what is maxp here that we're missing...

[ZFTurbo]

@mrpossible, can you please provide additional details on problem. Did you compile already generated code from repository or newly generated by Python script?

Also please check our guide about compilation: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/README_QUARTUS.md

[baogiadoan]

I both compile already generated code from repository and newly generated by Python script, and still get the same error message.

Error (12006): Node instance "maxpooling" instantiates undefined entity

"maxp". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

It seems that the entity maxp in your file isn't defined or missing somethings.

On Sun, 6 Jan 2019 at 04:13, ZFTurbo notifications@github.com wrote:

@mrpossible https://github.com/mrpossible, can you please provide additional details on problem. Did you compile already generated code from repository or newly generated by Python script?

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[baogiadoan]

The issue was fixed, it's due to the file maxpool.v is not correctly added in the project, I've solved it, thanks :)

[baogiadoan]

No. The py code create full verilog description of neural net, including convolution blocks, other layers description, control module etc.

Do you use any converting tool to generate Verilog code from Python or you hard-code the whole verilog code for the Neural Net?