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ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA
Apache License 2.0
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Some problems with reading verilog code #26

Closed kangliyu1 closed 2 years ago

kangliyu1 commented 2 years ago

Hello, I found it difficult to understand some of the details in the process of reading the verilog code. Do you have any suggestions? Do you have information on the role of each module's signal ports? (For example, the role of each signal port of maxp, the role of the border module, etc.) I hope you can give me some pointers, thank you very much! !

MaKaRoIIIKa commented 2 years ago

Hello, @kangliyu1 ! I am preparing a document for you with module pin assignments. It will take some time, you will have to wait.

kangliyu1 commented 2 years ago

Hello, @kangliyu1 ! I am preparing a document for you with module pin assignments. It will take some time, you will have to wait.

Thank you so much! ! ! Thank you so much! ! ! Thank you so much! ! !

ZFTurbo commented 2 years ago

We prepeared documentation with description of each pin for every module in project. Feel free to ask any question.

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/docs/modules_pins_eng.docx

kangliyu1 commented 2 years ago

We prepeared documentation with description of each pin for every module in project. Feel free to ask any question.

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/docs/modules_pins_eng.docx

You helped me a lot, thank you so much