The verilog project fails under higher clock frequencies (use PLL frequency multiplication 100MHz), and the FPGA output is not as expected

ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

Apache License 2.0

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The verilog project fails under higher clock frequencies (use PLL frequency multiplication 100MHz), and the FPGA output is not as expected #29

Open MisRight opened 2 years ago

MisRight commented 2 years ago

First of all, this project is really good. I admire you for doing such an excellent job and very interested in your work. I want to ask you some questions. I tested whether the project works under different system clocks, and found that it can only run normally at 50Mhz or lower frequency. If I use 100Mhz system clock, the output result is unstable or even wrong. How can i solve this problem? I hope to get your guidance, thank you very much anyway.

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