ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA
Apache License 2.0
291 stars 88 forks source link

Convert_image_for_testbench.py #32

Closed ECEVLSIWorld closed 1 year ago

ECEVLSIWorld commented 1 year ago

Dear sir, Thanks for your code ,it is really helpful for me ,but I have a doubt in convert_image_for_testbench.py codes .I have to give test image number as 2 ,but default it is 0 ,i don't have an idea to change the code for giving test image as 2 , could you please help me to solve this problem.