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ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA
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convert_image_for_testbench.py #33

Closed ECEVLSIWorld closed 1 year ago

ECEVLSIWorld commented 1 year ago

Dear sir, Thanks for your code ,it is really helpful for me ,but I have a doubt in convert_image_for_testbench.py codes I have to give test image number as 2 ,but default it is 0 ,i don't have idea to change the code for giving test image as 2 , could you please help me to solve this problem.

ZFTurbo commented 1 year ago

Can you please write mode deatils? We couldn't understand wht the problem is.

ECEVLSIWorld commented 1 year ago

Sir ,i have to generate image 2 as test bench value to top module,so in convert image to test bench .py file consists only for image 0 conversation,but I need image 2 ,so which Line in the code should be modified to get the test image 2 values

On Mon, 19 Dec, 2022, 2:26 pm Roman Solovyev, @.***> wrote:

Can you please write mode deatils? We couldn't understand wht the problem is.

— Reply to this email directly, view it on GitHub https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33#issuecomment-1357305341, or unsubscribe https://github.com/notifications/unsubscribe-auth/A42O7O6MX5MS4F7T35DXK6LWOAPM3ANCNFSM6AAAAAATCM5DOM . You are receiving this because you authored the thread.Message ID: <ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33/1357305341 @github.com>

ECEVLSIWorld commented 1 year ago

Please reply soon sir

On Mon, 19 Dec, 2022, 2:30 pm prakadeesh prakadeesh, < @.***> wrote:

Sir ,i have to generate image 2 as test bench value to top module,so in convert image to test bench .py file consists only for image 0 conversation,but I need image 2 ,so which Line in the code should be modified to get the test image 2 values

On Mon, 19 Dec, 2022, 2:26 pm Roman Solovyev, @.***> wrote:

Can you please write mode deatils? We couldn't understand wht the problem is.

— Reply to this email directly, view it on GitHub https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33#issuecomment-1357305341, or unsubscribe https://github.com/notifications/unsubscribe-auth/A42O7O6MX5MS4F7T35DXK6LWOAPM3ANCNFSM6AAAAAATCM5DOM . You are receiving this because you authored the thread.Message ID: <ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33/1357305341 @github.com>

ZFTurbo commented 1 year ago

Run converter with python convert_image_for_testbench.py --use_image 2

ECEVLSIWorld commented 1 year ago

It's not changing sir ,i have tried, could you please mention line number

On Mon, 19 Dec, 2022, 2:34 pm Roman Solovyev, @.***> wrote:

Run converter with python convert_image_for_testbench.py --use_image 2

— Reply to this email directly, view it on GitHub https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33#issuecomment-1357315804, or unsubscribe https://github.com/notifications/unsubscribe-auth/A42O7O42F6LWE56AW2SBYLLWOAQKVANCNFSM6AAAAAATCM5DOM . You are receiving this because you authored the thread.Message ID: <ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33/1357315804 @github.com>

ZFTurbo commented 1 year ago

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/utils/convert_image_for_testbench.py#L127

You can add after line 127: use_image = 2

ECEVLSIWorld commented 1 year ago

Sir after changing also ,iam got same answer

On Mon, 19 Dec, 2022, 3:01 pm Roman Solovyev, @.***> wrote:

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/utils/convert_image_for_testbench.py#L127

You can add after line 127: use_image = 2

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MaKaRoIIIKa commented 1 year ago

https://drive.google.com/file/d/1dBpfz9BrU0x2I-VMU-TdY8-5aVhH8tLU/view?usp=share_link

ECEVLSIWorld commented 1 year ago

Thanks a lot. Sir

On Mon, 19 Dec, 2022, 4:15 pm MaKaRoIIIKa, @.***> wrote:

https://drive.google.com/file/d/1dBpfz9BrU0x2I-VMU-TdY8-5aVhH8tLU/view?usp=share_link

— Reply to this email directly, view it on GitHub https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33#issuecomment-1357447124, or unsubscribe https://github.com/notifications/unsubscribe-auth/A42O7O2Z73UJG77SYHJABKLWOA4ERANCNFSM6AAAAAATCM5DOM . You are receiving this because you authored the thread.Message ID: <ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/issues/33/1357447124 @github.com>