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ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA
Apache License 2.0
291 stars 88 forks source link

cam_proj.out.sdc #5

Open hooper888 opened 5 years ago

hooper888 commented 5 years ago

Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

Hello, there is no file cam_proj.out.sdc. And this series of errors appears, please help !!!

ZFTurbo commented 5 years ago

It's not errors it's warnings. It must work without this file (we don't have it also).

albertlu2013 commented 5 years ago

Hi ZFTurbo I get the same Critical Warning. The programmer is 100% success. But my board can not work. The ili9341 lcd is all white (only back led light). I found the "TimeQuest Timing Analyzer" is red color. Is your "TimeQuest" also red ?

Thanks

ZFTurbo commented 5 years ago

Timing requirements not met - this typically means that frequencу is too high, try to decrease it until this warning is gone. But we also have this warning. TimeQuest Timing Analyzer currently green for us.

Regarding white screen: May be screen connection is incorrect?

I will have access to hardware device at monday. It currently successfully work with files from repo, but I will check log of compilation to see the possible problems.

ZFTurbo commented 5 years ago

Screen from Quartus. Project is ok with these warnings.

https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/master/images/Q-scr-2019-02.png