This is supposed to be a pure module structure re-organize in order to reduce name collision, but nevertheless i fix some bugs along the way:
Data.XX are renamed to Std.Data.XX
System.IO.XXX are renamed to Std.IO.XX
Add more prim array / vector quoters.
Fix a issue where we release slot too early, which can create a race condition with previously haskell thread which is about to takeMVar but interrupted by RTS.
Now we read async I/O result inside manager step and directly unlock waiting thread with results, thus no need for them to peek buffer_size_table.
This is supposed to be a pure module structure re-organize in order to reduce name collision, but nevertheless i fix some bugs along the way:
Data.XXare renamed toStd.Data.XXSystem.IO.XXXare renamed toStd.IO.XXtakeMVarbut interrupted by RTS.stepand directly unlock waiting thread with results, thus no need for them to peekbuffer_size_table.