Closed Jiahua-Gong closed 4 years ago
Those should be defined in the packages, are you including everything into the project?
On Thu, Mar 5, 2020 at 2:12 AM Jiahua notifications@github.com wrote:
HI ,,, I use cadence irun tool to compile this project. I find some error about like as follows . parameter DAT_BYTS, parameter CTL_BITS, ....
Thanks.
— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/ZcashFoundation/zcash-fpga/issues/9?email_source=notifications&email_token=ABO2KOYOZP6CC7I47GUYEZTRF4C73A5CNFSM4LCAESLKYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4ISUG7YA, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABO2KOYISXNH5RGYTJZJM5TRF4C73ANCNFSM4LCAESLA .
Systemverilog LRM says it writes parameter DAT_BYTS=value,package can override the value.if write parameter DAT_BYTS, it will be error.
Sorry I don't understand the error - in Vivado you shouldn't get errors if you add all the sources. The parameter DAT_BYTS will be correctly overridden by the top level system verilog file.
HI ,,, I use cadence irun tool to compile this project. I find some error about like as follows . parameter DAT_BYTS, parameter CTL_BITS, ....
Thanks.