Closed Amri95 closed 2 years ago
Sorry, it has been a long time since the last time I saw my github project. I can not see your figure here. I hope you have solved all your problems, but if you haven't yet or there are some more problems, you could connect me by email: zhaoqxcn@qq.com. I hope it would be helpful to you.
I couldn't get the driver files after the completion of the export RTL. so while loading ip into vivado tool. I got this error shown in the figure. And not able to generate .bit and .tcl file. Please suggest the solution for it. I am new to FPGA. Thankyou, Best regards