Closed NeuerUser closed 5 years ago
Yes.
Large portions of the design are working already, and should be checked in.
I'm still testing the flash memory using my new flash driver, but haven't (yet) gotten to either the SDRAM or the SPI-based accelerometer.. Those remain on my to-do list. The CPU should be able to work as is though.
Still need to figure out how to package the various Altera/Intel specific primitives. Those are likely to slow you down.
Hi Dan
That sounds like pretty good news. I would love to play around with it. Looking forward to anything you release.
Thanks again for your hard work!
Michael
I threw in the two altera primitives, so feel free to try out the project with them.
I still don't have the SDRAM memory working (yet), but the CPU should be in working order.
Dan
Thanks. That helps a lot. SDRAM would be nice, but it would alrady be great to get it working even without. I will see if I can get it compiled and running on the board. It is such a nice, small and inexpensive board.
The good news is that I already have the SDRAM controller, I just need to port it from another one of my designs to this one and get it up and running.
That's very nice, indeed. That would mean it could be a fully featured Soc .)
The ZipCPU now works on this board. I still need to get the SDRAM and MEMs sensor running, but the CPU itself is running.
To use, load the design onto your board, and then run (from sw/host) "zipload -r ../board/cputest". While it is loading, telnet into port 6956 (one greater than FPGAPORT in sw/host/port.h). Once the zipload program has loaded the CPU test program into the flash, you'll see a report in your telnet window.
I also got this board to learn about FPGA. It would be too great to also have the ZipCPU on this board. But it looks very daunting to me. Do you think you can get it working?
Cheers
Michael