[Enforcement] Variable defined before used in hbconsole.v.

[dh73]

According to the Verilog LRM (IEEE Std 1800™-2012) Section 6.5, all variables must be declared before they are used, apart from implicit nets. Without the `default_nettype set to none, the variable ps_full could be inferred as a local net by different synthesis tools.

This line uses ps_full before is declared. Lines 156 to 170 of hbconsole.v can be moved above this declaration to accomplish the design intent.

[dh73]

Same case with maintenance in line 227 (and 250) used in dualflexpress.v

And r_zero in line 104 of ziptimer.v

[ZipCPU]

Thanks! I created a pull request to capture these changes. See #12

Do you have any suggestions for finding these sorts of problems? Neither Verilator nor yosys seem to be giving me warnings. Thanks