Error (12006): Node instance "dspi_ddr_csn" instantiates undefined entity "altoddr".

[NeuerUser]

I am still very new to FPGAs and your AutoMake powered designs in special. So, please bear with me.

When I try to import this design into quartus, I get the following errors on design analysis:

Error (12006): Node instance "dspi_ddr_csn" instantiates undefined entity "altoddr". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "dspi_ddr_sck" instantiates undefined entity "altoddr". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "dspi_d0" instantiates undefined entity "addrio". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "dspi_d1" instantiates undefined entity "addrio". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

This seems to emenate from the toplevel.v file, where there are the following instatiations:

    // Wires for setting up the QSPI flash wishbone peripheral
    //
    //
    // QSPI)BMOD, Dual SPI bus mode, Bus modes are:
    //  0?  Normal serial mode, one bit in one bit out
    //  10  Dual SPI mode, going out
    //  11  Dual SPI mode coming from the device (read mode)
    altoddr dspi_ddr_csn(
        .outclock(s_clk),
        .din({(2){ w_dspi_cs_n}}),
        .pad_out(o_dspi_cs_n));
    altoddr dspi_ddr_sck( .outclock(s_clk),
        // .din({ !w_dspi_sck, 1'b1 }),
        .din({(2){w_dspi_sck}}),
        .pad_out(o_dspi_sck));
    addrio  dspi_d0(.inclock(s_clk), .outclock(s_clk),
            .dout({dspi_datp[0], dspi_datn[0]}),
            .din({(2){o_dspi_dat[0]}}),
            .pad_io(io_dspi_dat[0]),
            .oe(!dspi_bmod[0]));
    addrio  dspi_d1(.inclock(s_clk), .outclock(s_clk),
            .dout({dspi_datp[1], dspi_datn[1]}),
            .din({(2){o_dspi_dat[1]}}),
            .pad_io(io_dspi_dat[1]),
            .oe((dspi_bmod == 2'b10)?1'b1:1'b0));

What am I missing here? Where do I find these modules?

Thanks!

[ZipCPU]

There are actually three modules you need. One of them is addrio, another is altoddr, the third appears to be in the repository although I'm not (yet) certain if it is usable or not. addrio.v and altoddr.v are both files generated by Quartus for handling the high speed I/O used by the flash controller. I just placed them into the rtl/common directory. When Quartus builds them, they come with a bunch of other baggage that (hopefully) you won't need. Feel free to try them out and see how far you can get with them, while I see if I can't remove them somehow.

Incidentally, the goal is to be able to build this project with Yosys and ... those Quartus generated files are somewhat keeping me from this.

Dan

[NeuerUser]

Hi Dan

Thanks for your help. Unfortunately, I still wasn't able to get the design compiled. I guess that's mostly because of my missing knowledge. Here is what I experienced:

1. There were error messages within genpll.v about the parameters "altpll_component.clk1_divide_by", "altpll_component.clk1_duty_cycle", "altpll_component.clk1_multiply_by" and "altpll_component.clk1_phase_shift" not being formal parameters. I could work around this by commenting out these options.
2. Then the compilation went one step further, this time complaining that the module "altera_gpio_lite" is missing. I got the impression that this is needed for addrio and altoddr. So, I took a deeper look at these two and recreated them with the altera IP generator.
3. While this worked finally, I still get errors now about port inputs not being proper clock sources. These ports seem to be ports from underlying components of the altera_gpio_lite. They look like this:

Error (16080): Input port CLKHI of "altoddr:dspi_ddr_sck|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source.
Error (16081): Input port CLKLO of "altoddr:dspi_ddr_sck|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16082): Input port MUXSEL of "altoddr:dspi_ddr_sck|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16080): Input port CLKHI of "altoddr:dspi_ddr_csn|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source.
Error (16081): Input port CLKLO of "altoddr:dspi_ddr_csn|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16082): Input port MUXSEL of "altoddr:dspi_ddr_csn|altera_gpio_lite:altoddr_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16080): Input port CLKHI of "addrio:dspi_d1|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source.
Error (16081): Input port CLKLO of "addrio:dspi_d1|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16082): Input port MUXSEL of "addrio:dspi_d1|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16080): Input port CLKHI of "addrio:dspi_d0|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source.
Error (16081): Input port CLKLO of "addrio:dspi_d0|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..
Error (16082): Input port MUXSEL of "addrio:dspi_d0|altera_gpio_lite:addrio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio"  must be connected with a proper clock source..

I guess, I am currently at the end of my understanding. Do you have any idea what is missing?

[NeuerUser]

small update:

I followed the signals from the error messages up to the toplevel. In the end the messages seem to complain (if I understand it correctly), that 's_clk' is not a proper clock source for the altera_gpio_lite module and its submodules.

I will see if it helps if I recreate the genpll module.

[NeuerUser]

Doesn't help. If I recreate the genpll module, I am back to the original error messages complaining about the formal parameters:

Error (10130): Verilog HDL error at genpll.v(101): parameter "clk1_divide_by" is not a formal parameter of instantiated module
Error (10130): Verilog HDL error at genpll.v(102): parameter "clk1_duty_cycle" is not a formal parameter of instantiated module
Error (10130): Verilog HDL error at genpll.v(103): parameter "clk1_multiply_by" is not a formal parameter of instantiated module
Error (10130): Verilog HDL error at genpll.v(104): parameter "clk1_phase_shift" is not a formal parameter of instantiated module
Error (12152): Can't elaborate user hierarchy "genpll:genclk"

Which I find strange, as Quartus itself has generated the file. So, why should it then complain about it... Very strange...

[NeuerUser]

OK, SUCCESS! I found the culprit. There was a (maybe leftover) file called "altpll.v", which seemed to interfere. As soon, as I removed it from the project, compilation went through (and I could also keep the above mentioned parameters). I don't think that the error messages I got were very helpful. The only thing they told me were that it had something to do with a clock source.

Ok, now I will see if I can get it running on the board and how to interact with it via the debug interface.

[NeuerUser]

btw: Flow Status Successful - Tue Mar 5 11:31:36 2019 Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Revision Name ArrowZip Top-level Entity Name toplevel Family MAX 10 Device 10M08SAU169C8G Timing Models Final Total logic elements 4,987 / 8,064 ( 62 % ) Total registers 2717 Total pins 16 / 130 ( 12 % ) Total virtual pins 0 Total memory bits 297,984 / 387,072 ( 77 % ) Embedded Multiplier 9-bit elements 16 / 48 ( 33 % ) Total PLLs 1 / 1 ( 100 % ) UFM blocks 0 / 1 ( 0 % ) ADC blocks 0 / 1 ( 0 % )

[NeuerUser]

closing this issue as it is solved now (other open points in new issues)

[ZipCPU]

Thanks for closing the issue, although I will note that the problem still isn't really solved. My goal is that you should be able to build this design without needing to use the Altera IP generator.

Keep your eyes peeled, I might be able to offer that in the near future.

[NeuerUser]

That would be great. I am not really a fan of Altera's IP generator. :+1: