aximwr2wbsp increments address too early, first data written to the next incremented address

ZipCPU / wb2axip

Bus bridges and other odds and ends

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aximwr2wbsp increments address too early, first data written to the next incremented address #25

Closed motylewski closed 4 years ago

motylewski commented 4 years ago

Simulated using Vivado 2019.2 AXI Verification IP 1.1 Data is always landing in incremented address. Both in HW and in the simulation.

In the test mit HW single write there is the same problem - writing to addr+1 instead of addr. aximwr2wbsp-bug4

ZipCPU commented 4 years ago

I think I see it.

Check this patch, and see if it fixes your issue.

Dan

motylewski commented 4 years ago

Simulation looks OK now, thanks ! In HW also OK now. But there is (and always was) another issue: endianess is swapped when writing. Reading is OK. Because of some reasons aximwr2wbsp has OPT_SWAP_ENDIANNESS = 1'b1 (I do not need it) while aximrd2wbsp OPT_SWAP_ENDIANNESS = 0 (works OK).

aximwr2wbsp-fixed

ZipCPU commented 4 years ago

Fixed in 864d554.

Dan

motylewski commented 4 years ago

OK, thanks. As for OPT_SWAP_ENDIANNESS I have added that into axim2wbsp so it is adjustable in the same way for both WR and RD channels. I am using 0 there anyway.