Verilog Syntax Errors When Synthesizing ZBasic in Quartus

[jdssnag1]

Right now I am trying my best to implement the ZBasic system on a DE10-Nano development kit. After I used AutoFPGA (to modify the amount of block RAM and change the clock speed to 50MHz) I was successfully able to simulate the design using Verliator, but I am running into synthesis errors when I bring the RTL files into a Quartus project. Below is an image of the synthesis errors I am getting: The Quartus (17.1) project is set up where only all of the Verilog files from the RTL directory from ZBasic are included and "toplevel.v" is the top-level entity. If it means anything, I was able to get just the ZipCpu to synthesize properly in Quartus using a similar project structure. I would greatly appreciate some help getting this figured out or some advice to get pushed in the right direction. So sorry if I missed something simple. Been beating my head over this the past couple of days!

[ZipCPU]

Thanks for the report. I'm aware of the problem from other projects, but just don't do enough Quartus work to iron out all the wrinkles. The basic problem is that generic blocks require names. So, for example:

generate if (gk=0; gk<NS; gk=gk+1)
begin
    // some logic
end endgenerate

will generate an error, whereas,

generate if (gk=0; gk<NS; gk=gk+1)
begin : NAMED_BLOCK
    // some logic
end endgenerate

will pass. Now I just have to go through the design finding all of the unnamed blocks, name them, and hope I got them right (since I'm not using Quartus to know) ... But in general the fix really is that simple.

Dan

[jdssnag1]

Hi Dan,

It looks like the syntax issue were as simple as you described in the last post. Added some generic block names and the errors are gone. Thanks so much for the help! I'm more of a VHDL guy than Verilog so those kinds of errors easily get past me.

After that was fixed I ran into some syntax errors regarding missing end statements as shown below. I think these errors were due to lines 703-712 in wbxbar.v:

for(M=1; M<NS; M=M+1)
    always @(*)
    begin
        o_swe[M]            = o_swe[0];
        o_saddr[M*AW +: AW] = o_saddr[0 +: AW];
        o_sdata[M*DW +: DW] = o_sdata[0 +: DW];
        o_ssel[M*DW/8+:DW/8]= o_ssel[0 +: DW/8];
       end 

When I replaced those lines with:

for(M=1; M<NS; M=M+1)
    begin : WBXBAR_BLOCK7
        always @(*)
        begin
            o_swe[M]            = o_swe[0];
            o_saddr[M*AW +: AW] = o_saddr[0 +: AW];
            o_sdata[M*DW +: DW] = o_sdata[0 +: DW];
            o_ssel[M*DW/8+:DW/8]= o_ssel[0 +: DW/8];
        end
    end 

wbxbar.v synthesized without any errors. Should that change be fine?

Now I am getting only four errors when I synthesize the project after fixing syntax errors I only have four more remaining and I was curious if you had any idea of what could be causing them.

Error (10228): Verilog HDL error at spicmd.v(40): module "spicmd" cannot be declared more than once
Error (10228): Verilog HDL error at spirxdata.v(43): module "spirxdata" cannot be declared more than once
Error (10228): Verilog HDL error at spitxdata.v(41): module "spitxdata" cannot be declared more than once
Error (10228): Verilog HDL error at wbarbiter.v(61): module "wbarbiter" cannot be declared more than once

I have looked through all of the Verilog files in the project and I could not find any second declaration of these modules. If this also seems like a Quartus-dependent issue I can continue to look through it. Just thought I would see if you had any ideas on why these errors would be occurring. Thanks!

[ZipCPU]

Your change to wbxbar should be good.

As for the other, it looks like I may have left more than one copy of the spi*.v files in the repository. For now, just remove the extra files from main directory, keeping their counterparts in the sdspi/ subdirectory.

Dan

[ZipCPU]

Okay, I just updated the repository to remove the duplicate files. I've also placed an updated WBXBAR in there which should fix the errors you were receiving before.

Dan

[jdssnag1]

Awesome! Everything is synthesizing now on Quartus. Looks like removing those files did the trick. It totally got past me that duplicates of the files were in my project. Thanks for all of your help Dan!

[ZipCPU]

Glad I could help! Dan