Fix the testbench for zipmmu

[adwait]

I was having issues building the Verilator TB for zipmmu (issue #28). This PR details my fix. My system config is as follows:

OS: Ubuntu 18.04 on WSL2.0 Verilator version: Verilator 5.002 2022-10-29 rev v5.002-29-gdb39d70c7

Steps taken are as follows:

1. Run make verilator from $root/bench/rtl followed by make verilator from $root/sim/verilator. Error:

   zipmmu_tb.cpp:47:10: fatal error: Vzipmmu_tb.h: No such file or directory
   47 | #include "Vzipmmu_tb.h"
     |          ^~~~~~~~~~~~~~

2. Add BENCHOBJD include path to Makefile and #include "Vzipmmu_tb___024root.h" to zipmmu_tb.cpp.
3. Make signal naming changes to zipmmu_tb.cpp.
4. Fix the I/O port order in the Verilog testbench (zipmmu_tb.v)

[ZipCPU]

Unfortunately, the ZipMMU needs to be entirely rewritten. As of the more recent upgrade, it has become painfully clear that the ZipMMU (as written) has the wrong interfaces. It needs to match the interfaces driving both the prefetch and the memory unit, and therefore needs to act as a bump in the log between them.

Frankly, I'm more tempted to remove this (non-functional) MMU entirely, rather than to try to fix it.