Additional error-checking of pin assignments

[ZishuoYang]

Two categories of possible errors have been checked at the time the mapping Excel docs were finalized:

• Errors due to pin-assigning in the process of mapping each net/connection:

  1. Check that polarity is correct: _N/P of one pin matches _N/P of the other pin.
  2. Check if the mapped pins have the same type of signal ID: e.g. Pigtail's signal ID (ASIC_CH) agrees with DCB’s signal ID (DC_ELK).
  3. Check that connector pins in the two list match.
  4. Check if a specific pin on a specific connector is used more than once.

• Errors due to violating design rules, for each type of signals:

  1. Check the Elink Packing Order between EC_ELK and ASIC_CH
     • For each ASIC, find the 1st ELK and check that with increasing ASIC channel number, ELK channel number decreases.
  2. ~Check MC_SEC connects to EC_SEC~ (No longer used)
  3. Check MC_TFC connects to Hybrids on the assigned connectors the number of signals
  4. Check DC_OUT_RCLK (from DCs to Hybrids) on the assigned connectors and the number of signals
  5. Check EC_RESET connects to DC and Hybrids on the assigned connectors and the number of signals
  6. Check EC_HYB_i2C (from SCA to Hybrids) on the assigned connectors and the number of signals
  7. Check EC_ADC connects to Hybrid thermistors on the assigned connectors and the number of signals

[CoffeeIntoScience]

When you say, for example, that "MC_TFC connects to hybrids and the number of signals" does that mean you've checked that every 4-asic group gets one TFC assigned?

[ZishuoYang]

No it's more basic than that. At this stage I was more concerned with whether a signal has been assigned to the right connector. So the checks regarding the control signals (MC, EC, etc) were for example: if a TFC signal is from JD9/JD10 does it go to JP8/9/10/11? And count the number of TFC signals going to certain JPs and check that matches the way I assigned them.

I'll update the descriptions above.

Another example:

According to Documentation, DCBs(0,1,4,5,6,7,8,9,10) to 54 Hybrid sigs on PT and 20 DC sigs on DCB(0,1,4,5,6,7,8,9,10,11) 
            if SEAMSlot in [0]:
                if PtSlot not in [0,1] and DcbSlot not in [0]:
                    print('EC_ADC error in DCB(0)')
                    print(PtSlot, DcbSlot)
            elif SEAMSlot in [1]:
                if PtSlot not in [2,3] and DcbSlot not in [1]:
                    print('EC_ADC error in DCB(1)')        
            elif SEAMSlot in [4]:
                if PtSlot != -1 and DcbSlot not in [2]:
                    print('EC_ADC error in DCB(4)')        
            elif SEAMSlot in [5]:
                if PtSlot != -1 and DcbSlot not in [3]:
                    print('EC_ADC error in DCB(5)')
            elif SEAMSlot in [6]:
                if PtSlot not in [4,5] and DcbSlot not in [4,6]:
                    print('EC_ADC error in DCB(6)')
            elif SEAMSlot in [7]:
                if PtSlot not in [6,7] and DcbSlot not in [5,7]:
                    print('EC_ADC error in DCB(7)') 
            elif SEAMSlot in [8]:
                if PtSlot != -1 and DcbSlot not in [8,9]:
                    print('EC_ADC error in DCB(8)')
            elif SEAMSlot in [9]:
                if PtSlot not in [8,9] and DcbSlot != -1:
                    print('EC_ADC error in DCB(9)')
            elif SEAMSlot in [10]:
                if PtSlot not in [10,11] and DcbSlot not in [10,11]:
                    print('EC_ADC error in DCB(10)') 
            else:
                print('SCA assignment for EC_ADC not agree with Documentation')

[ZishuoYang]

does that mean you've checked that every 4-asic group gets one TFC assigned?

The way mapping was done made sure every 4-asic group gets one TFC assigned. It's also been checked by eye,

[ZishuoYang]

Review comments from Phoebe, Feb 18 2019. With my replies followed.

Regarding Backplane Error Checking. I am trying to think of any corner cases that could be missed based on the list Zishuo has shown me.

• Suppose a line appeared twice from a copy-paste error or (heaven forbid) all the way back in the original map: would it have been caught? (inverse of item 4 on #43 essentially)

We now agree that this type of error has been covered. - ZSY

• Is there any line its possible to have dropped? Say we go from ELK_CH11 - ELK_CH10 - ELK_CH8 stepping down. Does your check that the channel number decreases find if it skips one?

I have checked that within a subframe block (see figure below) the numbers do not skip. But we can check additionally between blocks. -ZSY

• Has any checking been done that every sense line finds its way to the telemetry connector one way or another? Is it possible to do so?
• Similar for the LV lines. Can we be sure that every one makes its way off the backplane either at one of these godawful swage connectors or to JPLx?

We agree that because pin assignments for LV are from the copy-paste lists, the thing to check instead should be Tom's definition of breakout assignment table. - ZSY

• I also put a couple clarifying questions on the issues themselves to make sure I understand what's been done

These have been answered. -ZSY

• It would be nice to also have a way to know for sure that all signals with a _P or _N received a label of DIFFPAIR or SE_DIFFPAIR, but it's not obvious this is possible

Possible, but need to add function in NetlistCheck.py for parsing the netlist to get this additional label. We now agree that this is low priority. - ZSY

[ZishuoYang]

We have implemented the following general checks:

• Check that all netnames from the pin-assignment copy-paste lists are present on the netlist generated from the schematics.

[ZishuoYang]

For @yipengsun to develop additional checking on the single-to-differential signals: