vexriscv DDR3 on tang primer 20k

[lk-davidegironi]

Hello,

I'm trying to make vexriscv work on Tang Primer 20k with DDR3. First I have to find timing for the SDRAM chip, which is the H5TQ1G63EFR. For this reason I've searched and find your project here.

I'm using the following config values which I suppose are ok for my IC, cause test ends with "Check Stage 1 Finished without Mismatch" and "Check Stage 2 Finished without Mismath".

I've just changed rowWidth: Int = 13 and colWidth: Int = 10. Cause my 64Mb x 16, should have row address from A0 to A12 and column address A0 to A9.

Am I right? Do you have any tips on making this works on vexriscv?

Thanks

case class slowDDR3Cfg(
    // Timing config
    // t means time, counted in ps
    tRTP: Int = 7500,
    tRP: Int = 12500,
    tWTR: Int = 7500,
    tRC: Int = 55000,
    tRAS: Int = 37500,
    tRCD: Int = 12500,
    tFAW: Int = 40000,
    tRRD: Int = 7500,
    tCKE: Int = 75000,
    tREFI: Int = 7800000,
    tRFC: Int = 160000,

    // n means clk count
    // for it's a slow DDR3, CAS is fixed 6
    nCAS: Int = 6,
    nDLLK: Int = 512,
    nZQInit: Int = 512,

    // Interface Config
    dqWidth: Int = 16,
    // bank Width is fixed 3
    rowWidth: Int = 13,
    colWidth: Int = 10,

    // DDR Clock Frequency, counted in MHz
    // It is half to the sys clk
    clkFreq: Int = 50,

    // use multiple counters could increase the frequency, but the size would be larger
    // TBD.
    multipleCounters: Boolean = false,

    // use burst could significantly increase the r/w rate to about 4 times, but the size would also be increased.
    // TBD.
    enableBursts: Boolean = false
) {}

[ZiyangYE]

Sorry, I currently don't have the board on hand, but I think the modification would work.

Additionally, the I/O performance of this project is significantly lower compared to conventional DDR3 interfaces. It seems fine for a DIY entertainment project. If you plan to use it with VexRISCV for production purposes, I would recommend using Gowin's IP and instantiating it using the blackbox feature of SpinalHDL.

[lk-davidegironi]

Thank you! I'm planning to use the spinal.lib.memory.sdram._ classes as used in Briey OS. But I'm new to SpinalHDL... I'm trying ...

[ZiyangYE]

Moreover, since the example is functional, another idea is to ignore the highest bit and only use the remaining address bits. This is also how the example determines whether the DRAM is 1Gb or 2Gb.

//Step 0: write at lower 1Gb int_app_addr<=27'h000_0000; app_wr_payload<=16'h5A01;

//Step 1: write at higher 1Gb int_app_addr<=27'h400_0000; app_wr_payload<=16'h5329;

//Step 2: read the lower 1Gb //If overwritten, it is 1Gb. Otherwise it is 2Gb int_app_addr<=27'h000_0000; ddr_size<=app_rd_payload==16'h5A01 ? DDR_SIZE_2G : DDR_SIZE_1G;

[ZiyangYE]

Thank you! I'm planning to use the spinal.lib.memory.sdram._ classes as used in Briey OS. But I'm new to SpinalHDL... I'm trying ...

Yeah, SpinalHDL is really powerful. But migrating from Verilog to it could be quite a task... To be honest, I'm not really familiar with it either...

[lk-davidegironi]

I'm not even familiar with soft cores. Sdram is for sure not the thing to start with, but I have to try.

[lk-davidegironi]

I'm moving to SDRAM which is natively supported by Briey. I've to buy the SDRAM PMOD from sipeed based on W9825G6KH (attached the schematic). Wondering if you can share the source scala file for the vexriscv cpu on tang primer 25k you have just poste here: https://github.com/ZiyangYE/LicheeTang25k_VexRV_micro/ Tang_sdram_xsds_V1.2_Schematic.pdf

[ZiyangYE]

I'm moving to SDRAM which is natively supported by Briey. I've to buy the SDRAM PMOD from sipeed based on W9825G6KH (attached the schematic). Wondering if you can share the source scala file for the vexriscv cpu on tang primer 25k you have just poste here: https://github.com/ZiyangYE/LicheeTang25k_VexRV_micro/ Tang_sdram_xsds_V1.2_Schematic.pdf

Sure. I've included that Scala file in the latest commit. But just a heads up, my softcore didn't use SDRAM. It's more about just compiling VexRV into a Verilog file and using it as if it were an IP.

Also, you can find a SDRAM controller for 25k in another example. The 100M branch seems more stable, while the 133M one has some timing issues, probably because my board is an ES version, which seems to have some differences from the production version.