Open ZoranStojsavljevic opened 5 years ago
Hello Zoran,
I'm having the exactly same problem trying to go from supervisor mode(b10011) to monitor mode.
how did you solve it?
Regards, Lucas Cunha
I did not solve it. Simply as that.
Zee
Well, I'm trying to trigger a binary file as a kernel using u-boot as a bootloader. I'm on supervisor mode, which seems to be necessary to write on C1(control register), but when i try to write on C1(control register) my program hangs.
Have you tried to make any changes on the cortex-a8 Control Register? If so, how did you do it?
I know it's not the topic of your post, but there are no information about this on an am335x with u-boot environment.
Regards, Lucas Cunha
Well, I'm trying to trigger a binary file as a kernel using u-boot as a bootloader. I'm on supervisor mode, which seems to be necessary to write on C1(control register), but when i try to write on C1(control register) my program hangs.
Have you tried to make any changes on the cortex-a8 Control Register? If so, how did you do it?
I know it's not the topic of your post, but there are no information about this on an am335x with u-boot environment.
Regards, Lucas Cunha
Hello Lucas,
I do not recall if I tried that. Suddenly I got to work on Android/kernel low level layers with i.MX6 and i.MX8 silicons, and this topic disappeared from my radar screen.
Nowadays what I do is just formally enhance bbb-yocto repo to newest YOCTO releases. Since I removed BBB platform from my desk, I was not able to check anything on the target.
If I return BBB back, I will try to check upon C1 control register.
Zoran
Hello Lucas,
I am exploring nowadays something else. And then I found something interesting,
The first pointer is here: https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-processor-modes?lang=en
Also here: https://www.embien.com/blog/arm-architecture-registers-exception-model
And the registers, for passing the arguments: https://www.cs.uaf.edu/2017/fall/cs301/lecture/11_17_syscall.html
Maybe for smc 0 (AM 335x syscall instruction) there are arguments missing???
Since as it hangs, the supplied # and args values might be wrong!
Zee
Usually I use off the shelf systems (various Linux distros) to set up the BBB, as referent systems design platform.
Recently, I have started to dive more deep into the armv7 A8 programming model. And I found confusing areas (I have concrete questions to ask).
Namely, I would like to read the Secure Configuration Register: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf#page=133
For this purpose, I wrote iny driver, which is presented here (cp15-spm.c). https://github.com/ZoranStojsavljevic/bbb-yocto/blob/master/Issues/LKM/cp15_Secure_Privileged_Mode/cp15_spm.c
While reading the first time CPSR register, I got the following value: 0x60000013 (b10011 Supervisor Mode) - I am root/superuser.
I tried to set CPSR mode (LSB 5 bits) to the b10110 Secure Monitor Mode, but it seems that with the above presented code I am NOT able to do that!
While executing the following code: asm volatile("mrc p15, 0, %0, c1, c1, 0" : "=r"(reg_value) ); printk(KERN_INFO "Secure Configuration Register data: 0x%08x\n", reg_value);Code
I've got the following: Internal error: Oops - undefined instruction: 0 [#1] ARM
The full log is presented here (cp15_spm_execution_traces.txt): https://github.com/ZoranStojsavljevic/bbb-yocto/blob/master/Issues/LKM/cp15_Secure_Privileged_Mode/cp15_spm_execution_traces.txt
Could you, please, show me the code snippet which switches Supervisor Mode to Secure Monitor Mode (if at all possible)?
Thank you! Zoran