Open GlenNicholls opened 4 years ago
Hi @GlenNicholls, for VHDL I created a pull request already, see #197 . Verilog is already supported, which should make it pretty easy to extended it for SystemVerilog as well.
Awesome, thanks @matzesc!
I'll get on these soon. Need to get a few fixes ready for a release but I shouldn't be too long. Perhaps this weekend
What is the status for VHDL?
@GlenNicholls there was another issue specifically for VHDL (#173 ). As I said in there, it's working for me.
When will support for VHDL be added (
.vhd
and.vhdl
)? I would guess this is similar to Ada, so probably not much work there. SystemVerilog (.sv
)should be the same as verilog.