Open nkraemer opened 3 years ago
Hi @nkraemer, I created already a pull request for SystemVerilog, see #199
Good to know @matzesc. I was unaware there was a pending pull request. I can see it's been pending since 2019. Do you know why it has not yet been accepted yet?
I hope this support is in the works. I assume it should be easy to add support for systemverilog since verilog is supported already.
Verilog is already supported, and it would be great if SystemVerilog had support too. It uses the same commenting format.