Open abhisheietk opened 7 years ago
@block def fsr(bit,lfsr,clk): @always_comb def tap(): bit.next = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1 @always(clk.posedge) def logic(): lfsr.next = (lfsr >> 1) | (bit << 15) return tap,logic
bit can be calculated directly accessing lfsr bits. like...
bit.next = (lfsr[0] ^ lfsr[2] ^ lfsr[3] ^ lfsr[5] ) & 1
shifting actually increase the size of implementation. bit access is simple and efficient in FPGA architecture. but in processors you have no choice except shift.
please confirm design is convertible.
bit can be calculated directly accessing lfsr bits. like...
shifting actually increase the size of implementation. bit access is simple and efficient in FPGA architecture. but in processors you have no choice except shift.
please confirm design is convertible.