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abs-tudelft / fletcher

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
https://abs-tudelft.github.io/fletcher/
Apache License 2.0
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Fletchgen does not exit if input file fails to open #189

Closed mbrobbel closed 5 years ago

mbrobbel commented 5 years ago

Fletchgen does not exit if the input file fails to open. Is this intended behavior?

[INFO ]: Loading RecordBatch(es) from asdf
[ERROR]: Could not open file for reading. asdf ARROW:[IOError: Failed to open local file 'asdf', error: No such file or directory]
[INFO ]: Creating SchemaSet.
[INFO ]: Generating Mantle...
[DEBUG]: MMIO Type already exists in default pool.
[INFO ]: Generating DOT output.
[INFO ]: DOT: Generating output for Graph: Mantle
[INFO ]: DOT: Generating output for Graph: asdf
[INFO ]: Generating VHDL output.
[INFO ]: VHDL: Transforming Component Mantle to VHDL-compatible version.
[INFO ]: VHDL: Generating sources for component Mantle
[DEBUG]: VHDL: Transforming Cerata graph to VHDL-compatible.
[DEBUG]: VHDL: Resolve port-to-port connections...
[DEBUG]: VHDL: Materialize stream abstraction...
[DEBUG]: VHDL:   Expanding type MMIO_A32_D32:Rec
[INFO ]: VHDL: Saving design to: ./vhdl/Mantle.vhd
[INFO ]: VHDL: Transforming Component asdf to VHDL-compatible version.
[INFO ]: VHDL: Generating sources for component asdf
[DEBUG]: VHDL: Transforming Cerata graph to VHDL-compatible.
[DEBUG]: VHDL: Resolve port-to-port connections...
[DEBUG]: VHDL: Materialize stream abstraction...
[INFO ]: VHDL: Saving design to: ./vhdl/asdf.vhd
[INFO ]: VHDL: Generated output for 2 graphs.
[INFO ]: Saving simulation top-level design to: ./vhdl/SimTop_tc.vhd
[DEBUG]: SIM: Generating MMIO writes for 0 RecordBatches.
[INFO ]: fletchgen completed.
johanpel commented 5 years ago

Although it still generates a valid design for whatever it can find, I'm sure the user didn't intend to get the resulting design, so I fixed it on #190