Fix clock assignments - Githubissues

abs-tudelft / fletcher

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

https://abs-tudelft.github.io/fletcher/

Apache License 2.0

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Fix clock assignments #250

Closed johanpel closed 3 years ago

johanpel commented 3 years ago

Cerata inserts signals between basically everything to prevent all sorts of annoying VHDL stuff from being a problem, but it shouldn't for clock signals.