Taking a sequence of 7 elements with dimensionality D = 1 over a physical stream with 4 element lanes and complexity C < 4:
Transfer 1:
[active, active, active, active
All lanes must be used, because stai must be 0, and endi must be N-1. (Because C < 5 and C < 6)
Transfer 2:
active, active, active], inactive ?
The data must be aligned to lane 0 (C < 6: stai must be 0)
The last of dimension 0 must be asserted on the third lane. (C < 4: It is illegal to assert the last bit for dimension 0 when the data of that lane is inactive.)
But also, the last of any dimension must actually be asserted on the fourth lane? (C < 8: last of lanes 0 through N-2 must be driven low. strb effectively doesn’t exist.)
Assumed/Suggested Fix
The key inconsistency is derived from:
C < 4 It is illegal to assert the last bit for dimension 0 when the respective data lane is inactive, except for empty sequences.
At C < 8, the last signal does not refer to specific data lanes, but operates on a per-transfer level. The intent of this rule is to prevent postponing the last signal, not to establish requirements for data lanes with respect to the last signal. Hence, the rule should probably be changed to say:
C < 4 It is illegal to assert the last bit for dimension 0 when the transfer data is inactive, except for empty sequences.
or
C < 4 It is illegal to assert any last bit when the transfer data is inactive, except for empty sequences.
Background
Using https://abs-tudelft.github.io/tydi/specification/physical.html#signals
For N lanes, indexed 0 through N-1: C < 8: All
lastbits for lanes 0 to N−2 inclusive must be driven low by the source, and may be ignored by the sink. C < 8: Allstrbbits must be driven to the same value by the source. The sink only needs to interpret one of the bits. (strbeffectively doesn't exist, except to indicate empty sequences) C < 6:staimust always be driven to 0 by the source, and may be ignored by the sink. (Elements are aligned to lane 0.) C < 5:endimust be driven to N−1 by the source whenlastis zero, and may be ignored by the sink in this case. (Effectively, all lanes must be used, except when transferring the end of a sequence.) C < 4: It is illegal to assert thelastbit for dimension 0 when the respective data lane is inactive, except for empty sequences. (Effectively,lastmay not be postponed.)Issue
Taking a sequence of 7 elements with dimensionality D = 1 over a physical stream with 4 element lanes and complexity C < 4:
Transfer 1:
[active, active, active, activeAll lanes must be used, because stai must be 0, and endi must be N-1. (Because C < 5 and C < 6)Transfer 2:
active, active, active], inactive? Thedatamust be aligned to lane 0 (C < 6: stai must be 0) Thelastof dimension 0 must be asserted on the third lane. (C < 4: It is illegal to assert the last bit for dimension 0 when thedataof that lane is inactive.) But also, the last of any dimension must actually be asserted on the fourth lane? (C < 8: last of lanes 0 through N-2 must be driven low. strb effectively doesn’t exist.)Assumed/Suggested Fix
The key inconsistency is derived from:
At C < 8, the
lastsignal does not refer to specific data lanes, but operates on a per-transfer level. The intent of this rule is to prevent postponing thelastsignal, not to establish requirements for data lanes with respect to thelastsignal. Hence, the rule should probably be changed to say:or