It is not clear whether "stai" and "endi" signals are significant when "strb" is low.

[matthijsr]

Issue

While https://abs-tudelft.github.io/tydi/specification/physical.html#data-signal-description indicates that stai and endi are redundant when C≥7 (which adds support for a per-lane strb (strobe) signal), it is not clear whether stai and endi are significant when strb is low, although this is implied.

At lower complexities (C<7) the strb signal still exists, but only as a single bit to indicate that the entire transfer's data is inactive.

For a concrete example, it is unclear what values stai and endi should have when transferring an "empty sequence".

Assumed/Suggested Fix

stai and endi are insignificant when the strb of that index's data lane is driven low. (Which at C < 7, means that stai and endi are insignificant altogether when strb='0'.)

Note/Potential Issue

Another potential issue might arise from a lack of clarity around stai and endi when C≥7. While the above data signal specification indicates that

while a source that desires individual control over the lanes and thus has C≥7 would probably always drive endi to N−1 and stai to 0, a sink with complexity C≥7 still needs to accept input from sources that do use endi and stai.

This does not clarify whether a source with C≥7 should employ endi and stai in such a way.

In the event that a source transfers stai: 0, endi: 0, strb: 11010 do the stai and endi signals take precedence? (I.e., only lane 0 is truly active.)

Now, what about: stai: 0, endi: 0, strb: 01010 Since lane 0 is now inactive, taking my suggested fix, stai and endi are insignificant and lanes 1 and 3 are active.

Hence, I propose specifying that "stai and endi are only significant when all strb bits are driven high" As this still allows for sources with C<7 to be compatible with sinks with C≥7, but does not allow for sources with C≥7 to create confusing transfers.