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vp8 decoder assembly alignment issue #432

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
What is the expected behavior? What do you see instead?
when i run vp8 decoder for arm cortex-a8 on real view debugger, in 
sixtappredict4x4_neon.asm file, secondpass_filter4x4_only assembly function has 
following code.
    sub             r0, r0, r1, lsl #1
    add             r3, r12, r3, lsl #5

    vld1.32         {d27[0]}, [r0], r1      ;load src data
 vector load instruction is giving exception when the address is unaligned.

 It should not give any exception, the code need to be modified to work  even for unaligned access.

But the same issue is not coming when i ran on pandaboard with linux image,why?

What version are you using? On what operating system?

libvpx-v1.0.0, windows 7 (ARM Real view debugger suite debugger)

Can you reproduce using the vpxdec or vpxenc tools? What command line are
you using?

Please provide any additional information below.

Original issue reported on code.google.com by satish...@gmail.com on 4 May 2012 at 4:27

GoogleCodeExporter commented 9 years ago 
Can we get more information on this bug? what kind of environment do you have?

Original comment by albe...@google.com on 10 May 2012 at 6:21

GoogleCodeExporter commented 9 years ago 
Unaligned access support is a requirement for the ARM version.
Have you initialized your cortex-a8 correctly to enable unaligned accesses? set 
U=1 and A=0 in CP15?

The reason why you dont get the exception on pandaboard is exactly this, it is 
initialized properly and unaligned accesses are handled correctly by the system.

What version of RVDS are you using?

Original comment by attilan...@google.com on 11 May 2012 at 5:51

GoogleCodeExporter commented 9 years ago 
Unaligned access support is a requirement for the ARM version.
Have you initialized your cortex-a8 correctly to enable unaligned accesses? set 
U=1 and A=0 in CP15?

The reason why you dont get the exception on pandaboard is exactly this, it is 
initialized properly and unaligned accesses are handled correctly by the system.

What version of RVDS are you using?

Original comment by attilan...@google.com on 11 May 2012 at 5:51

GoogleCodeExporter commented 9 years ago 
[deleted comment]
GoogleCodeExporter commented 9 years ago 
By default A=0 in cortex-a8 CP15 c1 control register.
But i am not finding U bit in CP15 c1 control register

I am using Metrowerks codewarrior IDE 5.7.0 compiler and RVDEBUG V3.0 service 
pack 1
simulator.

Original comment by satish...@gmail.com on 18 May 2012 at 4:20

GoogleCodeExporter commented 9 years ago 
My mistake, U bit is not anymore in Cortex.

"The MMU controls what type of memory the CPU sees at a particular address.  
There are three memory types: Normal, Device, and Strongly-Ordered.  Only 
Normal memory supports unaligned accesses.  So, in order to have unaligned 
accesses work on the Cortex-A8/9, the memory being accessed needs to be marked 
as Normal and the CP15 A bit must be 0."

I think there are RVDS examples of setting up MMU.

Original comment by attilan...@google.com on 18 May 2012 at 5:31

GoogleCodeExporter commented 9 years ago 
can you suggest any example ?

Original comment by satish...@gmail.com on 18 May 2012 at 6:53

GoogleCodeExporter commented 9 years ago 
the example i had in mind is actually in the ARM Profiler...xvid

Original comment by attilan...@google.com on 18 May 2012 at 7:11

GoogleCodeExporter commented 9 years ago

Original comment by attilan...@google.com on 30 May 2012 at 6:06

GoogleCodeExporter commented 9 years ago 
Please re-open if the ARM configuration you have does not work.

thanks

Original comment by albe...@google.com on 28 Mar 2013 at 10:17