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acmpesuecc / BareBones

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Testbench required: Implement a testbench for an accepted PR for #1 #2

Open skudlur opened 3 years ago

skudlur commented 3 years ago

Description

Write a testbench for the SystemVerilog code that is accepted in issue #1. Make sure to test it with RTL simulation and verify with the code from the issue.

Understanding code

Make sure to fork and clone the accepted PR from #1 and compile the .sv file once to check if it is working before writing the testbench.

Resources

Refer to this link to learn more about writing a testbench.

Bounty points allotted: 60+

If you face any issues or have any queries, do not hesitate to contact the maintainers. Happy contributing!

JoyenBenitto commented 3 years ago

hey I want to work on this

skudlur commented 3 years ago

Sure sir, good luck! ;)

Skanda-Prasad commented 3 years ago

Can I work on this?

skudlur commented 3 years ago

Sure @Skanda-Prasad, good luck!

Skanda-Prasad commented 3 years ago

Sure @Skanda-Prasad, good luck!

I have finished it and sent in a PR. Can you please check?