acmpesuecc / BareBones

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Testbench required: Implement a testbench for syncRAM.sv #3

Open skudlur opened 2 years ago

skudlur commented 2 years ago

Description

Write a testbench code for the syncRAM.sv. Make sure to attach the RTL simulation file if possible

Understanding code

Make sure to clone the repo and compile the syncRAM.sv once to check if it is working before writing the testbench.

Resources

Refer to this link to learn more about writing a testbench.

Bounty points allotted: 100+

If you face any issues or have any queries, do not hesitate to contact the maintainers. Happy contributing!

Skanda-Prasad commented 2 years ago

May I work on this issue?