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acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules
MIT License
1 stars 13 forks source link

Create Reduce 1's FSM #10

Closed alfadelta10010 closed 1 month ago

alfadelta10010 commented 1 month ago

Design File: 500 points

bunsamosa-bot[bot] commented 1 month ago

Thank you for opening this issue! A Maintainer will review it soon!

rithulkamesh commented 1 month ago

can I get assigned?

alfadelta10010 commented 1 month ago

!assign @rithulkamesh 60

rithulkamesh commented 1 month ago

can i get reassigned?

alfadelta10010 commented 1 month ago

!deassign

alfadelta10010 commented 1 month ago

!assign @rithulkamesh 30