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acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules
MIT License
1 stars 13 forks source link

Create N-bit ALU #12

Open alfadelta10010 opened 1 month ago

alfadelta10010 commented 1 month ago

Design: 50 points

bunsamosa-bot[bot] commented 1 month ago

Thank you for opening this issue! A Maintainer will review it soon!

Shresht-Ahuja commented 1 month ago

can i get assigned for this issue

alfadelta10010 commented 1 month ago

!assign @Shresht-Ahuja 45

alfadelta10010 commented 1 month ago

Done, you have 45 mins, @Shresht-Ahuja

bunsamosa-bot[bot] commented 1 month ago

Hey @alfadelta10010! The timer for the @Shresht-Ahuja to work on the issue has finished, deassign and assign a new contributor or extend the current timer. Contact maintainer leads if inactive @DedLad @polarhive @achyuthcodes30

alfadelta10010 commented 1 month ago

!deassign