acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules
MIT License
1 stars 13 forks source link

Create an 8-bit ALU #18

Open alfadelta10010 opened 1 month ago

alfadelta10010 commented 1 month ago

Design: 25 points

bunsamosa-bot[bot] commented 1 month ago

Thank you for opening this issue! A Maintainer will review it soon!

shubhangisrivastava04 commented 1 month ago

could you assign me to this please

alfadelta10010 commented 1 month ago

!assign @shubhangisrivastava04 45

alfadelta10010 commented 1 month ago

Done, @shubhangisrivastava04 you have 45 minutes

alfadelta10010 commented 1 month ago

!assign @shubhangisrivastava04 45

bunsamosa-bot[bot] commented 1 month ago

Hey @alfadelta10010! The timer for the @shubhangisrivastava04 to work on the issue has finished, deassign and assign a new contributor or extend the current timer. Contact maintainer leads if inactive @DedLad @polarhive @achyuthcodes30

shubhangisrivastava04 commented 1 month ago

!withdraw