coded the 32-bit- shift reg and test bench for it

acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules

MIT License

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Closed gaganbrwj closed 1 month ago

gaganbrwj commented 1 month ago

coded without using the in built shift library

bunsamosa-bot[bot] commented 1 month ago

Thank you from Opening this Pull Request, @gaganbrwj ! A Maintainer will review it soon!

alfadelta10010 commented 1 month ago

!bounty 10

bunsamosa-bot[bot] commented 1 month ago

Assigned 10 Bounty points to user @gaganbrwj !