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acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules

MIT License

1 stars 13 forks source link

Closed LalithaTanmayee closed 1 month ago

LalithaTanmayee commented 1 month ago

Uploaded Code, Test bench and RTL diagram of the Mealy FSM model

bunsamosa-bot[bot] commented 1 month ago

Thank you from Opening this Pull Request, @LalithaTanmayee ! A Maintainer will review it soon!

LalithaTanmayee commented 1 month ago

solves #9

alfadelta10010 commented 1 month ago

!bounty 450

bunsamosa-bot[bot] commented 1 month ago

Assigned 450 Bounty points to user @LalithaTanmayee !