acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules
MIT License
1 stars 13 forks source link

Create SISO shift register #6

Open alfadelta10010 opened 1 month ago

alfadelta10010 commented 1 month ago

Design File: 25 Points

H-Mudliar commented 1 month ago

Can i be assigned

alfadelta10010 commented 1 month ago

!assign @H-Mudliar 30

alfadelta10010 commented 1 month ago

@H-Mudliar very sorry, please do, you have 30 mins

bunsamosa-bot[bot] commented 1 month ago

Hey @alfadelta10010! The timer for the @H-Mudliar to work on the issue has finished, deassign and assign a new contributor or extend the current timer. Contact maintainer leads if inactive @DedLad @polarhive @achyuthcodes30

kevalpattani commented 1 month ago

can you please assign me this

alfadelta10010 commented 1 month ago

!deassign

alfadelta10010 commented 1 month ago

!assign @kevalpattani 30

alfadelta10010 commented 1 month ago

!deassign