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acmpesuecc / SystemVerilog-Playground

Various basic topics for SystemVerilog Modules
MIT License
1 stars 13 forks source link

Create SIPO shift register #7

Open alfadelta10010 opened 1 month ago

alfadelta10010 commented 1 month ago

Design File: 25 Points

kevalpattani commented 1 month ago

Hi, can you please assign me this issue !