acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

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Open skudlur opened 11 months ago

skudlur commented 11 months ago

Description

Add a testbench for sub_bytes.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

amrit-george commented 11 months ago

can i get assigned this issue?

ssether04 commented 11 months ago

can i get assigned if this is still open?