acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

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Open skudlur opened 8 months ago

skudlur commented 8 months ago

Description

You can use OpenLane2 to convert your Verilog file to a GDSII Layout file. You can refer to this

You are eligible to get brownie points if you document the optimizations done OpenLane2 and submit generated reports.

pranavacchu commented 8 months ago

can i get assigned?

ssether04 commented 8 months ago

can i get assigned if this is still open?

skudlur commented 8 months ago

@pranavacchu assigned

Alley2717 commented 8 months ago

can i try