Updated round.sv

[umarahmed10]

Original Code lacks a testbench for validation, incomplete connectivity, missing expected values, and lacks simulation. The updated code addresses these issues by introducing a comprehensive testbench that validates the "round" module's functionality. It includes a clock generation mechanism, input initialization, expected output values, and simulation commands. This makes the updated code effective for verifying the "round" module's behavior in a simulated environment.

[bunsamosa-bot[bot]]

Thank you from Opening this Pull Request, @umarahmed10 ! A Maintainer will review it soon!

[skudlur]

@umarahmed10 I expected a testbench for the design. round.sv is the design for which you need to write a testbench

[alfadelta10010]

Seeing no updates, this PR will be closed.