Testbench required for lastround.sv #4 Issue

acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

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Closed euphoricair7 closed 8 months ago

euphoricair7 commented 8 months ago

Added a Testbench to validate functionality for lastround.sv

bunsamosa-bot[bot] commented 8 months ago

Thank you from Opening this Pull Request, @euphoricair7 ! A Maintainer will review it soon!

alfadelta10010 commented 8 months ago

Duplicate PR as #17