[Updated] Logg : Added testbench to validate functionality in lastround.sv #4 Issue

acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

0 stars 7 forks source link

Closed euphoricair7 closed 8 months ago

euphoricair7 commented 8 months ago

Logg : Added testbench to validate functionality in lastround.sv Issue #4

bunsamosa-bot[bot] commented 8 months ago

Thank you from Opening this Pull Request, @euphoricair7 ! A Maintainer will review it soon!

alfadelta10010 commented 8 months ago

Your PR adds the Testbench to the design file, you need to create a separate file for it.

alfadelta10010 commented 8 months ago

@euphoricair7

Your instantiation of the testbench module has typos with ;
if (final_out == 128'hEXPECTED_RESULT) begin This line clearly has an error, there is no such variable.

As a result, you will not get complete points.

alfadelta10010 commented 8 months ago

!bounty 10

alfadelta10010 commented 8 months ago

!bounty 10

bunsamosa-bot[bot] commented 8 months ago

Assigned 10 Bounty points to user @euphoricair7 !