acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

0 stars 7 forks source link

Open skudlur opened 9 months ago

skudlur commented 9 months ago

Description

Add a testbench for aes_main.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

JiteshNayak2004 commented 8 months ago

heya can i get assigned to this issue

skudlur commented 8 months ago

@JiteshNayak2004 assigned

ssether04 commented 8 months ago

can i get assigned if this is still open?