acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

MIT License

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Open skudlur opened 1 year ago

skudlur commented 1 year ago

Description

Add a testbench for key_gen.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

amrit-george commented 1 year ago

can i be assigned this issue?

skudlur commented 1 year ago

@amrit-george assigned, please take one issue at a time

umarahmed10 commented 1 year ago

can i get assigned

vandanaj0110 commented 1 year ago

can I get assigned?

skudlur commented 1 year ago

@umarahmed10 assigned

skudlur commented 1 year ago

@amrit-george please tag the maintainer if you are not working on the issue. It is not good practice to unassign yourself

ssether04 commented 1 year ago

can i get assigned if this is still open?