acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog
MIT License
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Testbench required for mix_column.sv #5

Open skudlur opened 1 year ago

skudlur commented 1 year ago

Description

Add a testbench for mix_column.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

Notes:

cuber2116 commented 1 year ago

can you assign this to me?

skudlur commented 1 year ago

@Om210 assigned

ssether04 commented 1 year ago

can i get assigned if this is still open?

skudlur commented 1 year ago

@ssether04 assigned but stop spamming fgs

Shreevardhancoder commented 1 year ago

can i be assigned ?

skudlur commented 1 year ago

@Shreevardhancoder assigned

Alley2717 commented 1 year ago

can i try